Table of Contents
A Multicycle Data Path Implementation
Administrivia
Outline of Today’s Lecture
A Single Cycle Processor
Instruction Fetch Unit
The Main Control
Drawbacks of this Single Cycle Processor
Multiple Cycle Processor
Let’s design the multi-cycle data path…
The Five Steps of a Load Instruction
Multiple Cycle Datapath
Instruction Fetch Cycle: In the Beginning
Instruction Fetch Cycle: The End
1: Instruction Fetch Cycle: Overall Picture
2: Register Fetch / Instruction Decode
2: Register Fetch / Instruction Decode (Continue)
Instruction Decode: We have Beq
3: Branch Completion
2: Instruction Decode: We have a R-type!
3: R-type Execution
4: R-type Completion
2: Instruction Decode: We have an Ori!
3: Ori Execution
4: Ori Completion (keep control stable)
2: Instruction Decode: We have a Memory Access!
3: Memory Address Calculation
4: Memory Access for Store
4: Memory Access for Load
5: Write Back for Load
Putting it all together: Multiple Cycle Datapath
Putting it all together: Control State Diagram
Control design
Summary
Initial Representation: Finite State Diagram
Sequencing Control: Explicit Next State Function
Implementation Technique: Programmed Logic Arrays
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