2: Instruction Decode: We have an Ori!

• Next Cycle: Ori Execution

ExtOp=1

Ideal

Memory

WrAdr

Din

RAdr

32

32

32

Dout

MemWr=0

32

32

32

ALUOp=add

Instruction Reg

32

IRWr=0

32

Reg File

Ra

Rw

busW

Rb

5

5

32

busA

32

busB

RegWr=0

Rs

Rt

Rt

Rd

PCWr=0

ALUSelA

RegDst

32

PC

MemtoReg

32

0

1

2

3

4

16

Imm

32

ALUSelB=10

Mux

1

0

Zero

Zero

PCWrCond=0

PCSrc

BrWr=1

32

IorD

Func

Op

Control

6

6

Beq

Rtype

Ori

Memory

Previous slide

Next slide

Back to first slide

View graphic version