5: Write Back for Load

• Reg[rt] <- Mem Dout

Ideal

Memory

WrAdr

Din

RAdr

32

32

32

Dout

MemWr=0

32

32

32

ALUOp=Add

Instruction Reg

32

IRWr=0

32

Reg File

Ra

Rw

busW

Rb

5

5

32

busA

32

busB

RegWr=1

Rs

Rt

Rt

Rd

PCWr=0

ALUSelA=1

RegDst=0

32

PC

MemtoReg=1

ExtOp=1

32

0

1

2

3

4

16

Imm

32

ALUSelB=11

Mux

1

0

Zero

Zero

PCWrCond=0

PCSrc

BrWr=0

32

IorD=1

Func

Op

Control

6

6

Beq

Rtype

Ori

Memory

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