Write Buffer for Write Through

• A Write Buffer is needed between the Cache and Memory

  • Processor: writes data into the cache and the write buffer
  • Memory controller: write contents of the buffer to memory

• Write buffer is just a FIFO:

  • Typical number of entries: 4
  • Works fine if: Store frequency (w.r.t. time) << 1 / DRAM write cycle

• Memory system designer’s nightmare:

  • Store frequency (w.r.t. time) > 1 / DRAM write cycle
  • Write buffer saturation

Processor

Cache

Write Buffer

DRAM

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