Table of Contents
A Pipelined Processor
Outline of Today’s Lecture
Pipelining: Its Natural!
Sequential Laundry
Pipelined Laundry: Start work ASAP
Pipelining Lessons
Overview of a Multiple Cycle Implementation
Multiple Cycle Processor
The Five Stages of Load
Key Ideas Behind Instruction Execution Pipelining
Pipelining the Load Instruction
The Four Stages of R-type
Pipelining the R-type and Load Instruction
Important Observation
Solution: Delay R-type’s Write by One Cycle
The Four Stages of Store
The Four Stages of Beq
A Pipelined Datapath
The Instruction Fetch Stage
A Detail View of the Instruction Fetch Unit
The Decode / Register Fetch Stage
Load’s Address Calculation Stage
Load’s Memory Access Stage
Load’s Write Back Stage
A More Extensive Pipelining Example
Data Hazards
Data Hazard Solution: Register Forwarding
The Delay Branch Phenomenon
Reducing Branch delays (cont.)
The Delay Load Phenomenon
Delayed Load and Branch on a Real MIPS Processor
CPU design Summary
Single Cycle, Multiple Cycle, vs. Pipeline
Additional Notes
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