Multiple Cycle Processor

• MCP: If a functional unit is used more than once per instruction -> cannot pipeline -> lower performance

Ideal

Memory

WrAdr

Din

RAdr

32

32

32

Dout

MemWr

32

32

ALUOp

Instruction Reg

32

IRWr

32

Reg File

Ra

Rw

busW

Rb

5

5

32

busA

32

busB

RegWr

Rs

Rt

Rt

Rd

PCWr

ALUSelA

RegDst

32

PC

MemtoReg

ExtOp

32

0

1

2

3

4

Imm

32

ALUSelB

Mux

1

0

Zero

Zero

PCWrCond

PCSrc

BrWr

32

IorD

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