Table of Contents
Designing a Single Cycle Datapath
Outline of Today’s Lecture
What is Computer Architecture?
The Big Picture: Where are We Now?
The MIPS Instruction Formats
The MIPS Subset (We can’t implement them all!)
The Hardware “Program”
Combinational Logic Elements (Basic Building Blocks)
Storage Element: Register (Basic Building Block)
Storage Element: Register File
Storage Element: Idealized Memory
An Abstract View of the Implementation
Clocking Methodology
An Abstract View of the Critical Path
The Steps of Designing a Processor
Overview of the Instruction Fetch Unit
RTL: The ADD Instruction
RTL: The Load Instruction
RTL: The ADD Instruction
RTL: The Subtract Instruction
Datapath for Register-Register Operations
Register-Register Timing
RTL: The OR Immediate Instruction
Datapath for Logical Operations with Immediate
RTL: The Load Instruction
Datapath for Load Operations
RTL: The Store Instruction
Datapath for Store Operations
RTL: The Branch Instruction
Datapath for Branch Operations
Binary Arithmetics for the Next Address
Next Address Logic: Expensive and Fast Solution
Next Address Logic
RTL: The Jump Instruction
Instruction Fetch Unit
Putting it All Together: A Single Cycle Datapath
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