An Abstract View of the Critical Path

• Register file and ideal memory:

  • The CLK input is a factor ONLY during write operation
  • During read operation, behave as combinational logic:
    • Address valid => Output valid after “access time.”

Clk

5

Rw

Ra

Rb

32 32-bit

Registers

Rd

Clk

Data In

DataOut

Data

Address

Ideal

Data

Memory

Instruction

Instruction Address

Ideal

Instruction

Memory

Clk

PC

5

Rs

5

Rt

16

Imm

32

32

32

32

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