Datapath for Load Operations

• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5

5

5

Rw

Ra

Rb

32 32-bit

Registers

Rs

Rt

Don’t Care

(Rt)

Rd

RegDst

Extender

Mux

Mux

32

16

imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data In

WrEn

32

Adr

Data

Memory

32

ALU

MemWr

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