Putting it All Together: A Single Cycle Datapath

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

5

5

5

Rw

Ra

Rb

32 32-bit

Registers

Rs

Rt

Rt

Rd

RegDst

Extender

Mux

Mux

32

16

imm16

ALUSrc

ExtOp

Mux

MemtoReg

Clk

Data In

WrEn

32

Adr

Data

Memory

32

MemWr

ALU

Instruction

Fetch Unit

Clk

Zero

Instructionត:0>

Jump

Branch

• We have everything except control signals.

0

1

0

1

0

1

ច:25>

ក:20>

᝻:15>

ɘ:15>

Imm16

Rd

Rs

Rt

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