MSI Processor and Bus Actions
Processor:
- PrRd
- PrWr
- Writeback on replacement of modified block
Bus
- Bus Read (BusRd) Read without intent to modify, data could come from memory or another cache
- Bus Read-Exclusive (BusRdX) Read with intent to modify, must invalidate all other caches copies
- Writeback (BusWB) cache controller puts contents on bus and memory is updated
- Definition: cache-to-cache transfer occurs when another cache satisfies BusRd or BusRdX request