An example

Proc Action P1 State P2 state P3 state Bus Act Data from

1. P1 read u S -- -- BusRd Memory

2. P3 read u S -- S BusRd Memory

3. P3 write u I -- M BusRdX Memory or not

4. P1 read u S -- S BusRd P3’s cache

5. P2 read u S S S BusRd Memory

• Single writer, multiple reader protocol

• Why Modified to Shared?

• What if not in any cache?

  • Read, Write produces 2 bus transactions!

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