Logic Diagram of a Typical SRAM

• Write Enable is usually active low (WE_L)

• Din and Dout are combined to save pins:

  • A new control signal, output enable (OE_L) is needed
  • WE_L is asserted (Low), OE_L is disasserted (High)
    • D serves as the data input pin
  • WE_L is disasserted (High), OE_L is asserted (Low)
    • D is the data output pin
  • Both WE_L and OE_L are asserted:
    • Result is unknown. Don’t do that!!!

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