Write Buffer Saturation

• Store frequency (w.r.t. time) -> 1 / DRAM write cycle

  • If this condition exist for a long period of time (CPU cycle time too quick and/or too many store instructions in a row):
    • Store buffer will overflow no matter how big you make it
    • The CPU Cycle Time << DRAM Write Cycle Time

• Solution for write buffer saturation:

  • Use a write back cache
  • Install a second level (L2) cache:
  • store compression

Processor

Cache

Write Buffer

DRAM

Processor

Cache

Write Buffer

DRAM

L2

Cache

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