Address Translation and Caches
Where is the TLB wrt the cache?
What are the consequences?
Most of today’s systems have more than 1 cache
- Digital 21164 has 3 levels
- 2 levels on chip (8KB-data,8KB-inst,96KB-unified)
- one level off chip (2-4MB)
Does the OS need to worry about this?
page coloring = careful selection of va->pa mapping