1: Instruction Fetch Cycle: Overall Picture

Ideal

Memory

WrAdr

Din

RAdr

32

32

32

Dout

MemWr=0

32

32

32

ALUOp=Add

Instruction Reg

IRWr=1

32

32

busA

32

busB

PCWr=1

ALUSelA=0

Mux

0

1

32

PC

Mux

0

1

32

0

1

2

3

4

ALUSelB=00

Zero

Zero

PCWrCond=x

PCSrc=0

BrWr=0

32

IorD=0

Mux

1

0

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