Instruction Fetch Cycle: The End

• Every cycle ends AT the next clock tick (storage element updates):

  • IR <-- mem[PC] PCត:0> <-- PCត:0> + 4

Clk

Ideal

Memory

WrAdr

Din

RAdr

32

32

32

32

Dout

MemWr=0

PC

32

32

Clk

32

32

ALUOp = Add

4

Instruction Reg

IRWr=1

PCWr=1

Clk

You are here!

One “Logic” Clock Cycle

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