DRAM Read Timing

A

D

OE_L

256K x 8

DRAM

9

8

WE_L

CAS_L

RAS_L

• Every DRAM access begins at:

  • The assertion of the RAS_L
  • 2 ways to read: early or late v. CAS

OE_L

A

Row Address

WE_L

Junk

Read Access

Time

Output Enable

Delay

CAS_L

Col Address

Row Address

Junk

Col Address

D

High Z

Data Out

DRAM Read Cycle Time

Early Read Cycle: OE_L asserted before CAS_L

Late Read Cycle: OE_L asserted after CAS_L

Junk

Data Out

High Z

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