DRAM Write Timing

A

D

OE_L

256K x 8

DRAM

9

8

WE_L

CAS_L

RAS_L

• Every DRAM access begins at:

  • The assertion of the RAS_L
  • 2 ways to write: early or late v. CAS

WE_L

A

Row Address

OE_L

Junk

WR Access Time

WR Access Time

CAS_L

Col Address

Row Address

Junk

Col Address

D

Junk

Junk

Data In

Data In

Junk

DRAM WR Cycle Time

Early Wr Cycle: WE_L asserted before CAS_L

Late Wr Cycle: WE_L asserted after CAS_L

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