SPARCstation 20’s Memory System Overview
Memory Bus (SIMM Bus) 128-bit wide datapath
Memory
Controller
Memory Module 0
Processor Bus (Mbus) 64-bit wide
Memory Module 1
Memory Module 2
Memory Module 3
Memory Module 4
Memory Module 5
Memory Module 6
Memory Module 7
Processor Module (Mbus Module)
External
Cache
SuperSPARC Processor
Instruction
Cache
Data
Cache
Register
File
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