Fast Memory Systems: DRAM specific
Multiple RAS accesses: several names (page mode)
- 64 Mbit DRAM: cycle time = 100 ns, page mode = 20 ns
New DRAMs?
- Synchronous DRAM: Provide a clock signal to DRAM, transfer synchronous to system clock
- RAMBUS: reinvent DRAM interface (Intel will use it)
- Each Chip a module vs. slice of memory
- Short bus between CPU and chips
- Does own refresh
- Variable amount of data returned
- 1 byte / 2 ns (500 MB/s per chip)
- Cached DRAM (CDRAM): Keep entire row in SRAM, Gershon Kedem