Logic Diagram of a Typical DRAM
Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low
Din and Dout are combined (D):
- WE_L is asserted (Low), OE_L is disasserted (High)
- D serves as the data input pin
- WE_L is disasserted (High), OE_L is asserted (Low)
Row and column addresses share the same pins (A)
- RAS_L goes low: Pins A are latched in as row address
- CAS_L goes low: Pins A are latched in as column address
- RAS/CAS edge-sensitive